1. Field
The following description relates to a CMOS inverter circuit device. The following description also relates to a CMOS inverter circuit device that makes a circuit constitution simpler and also prevents generation of a short circuit current by simultaneously turning-off a P-type metal-oxide-semiconductor (PMOS) and an N-type metal-oxide-semiconductor (NMOS) included an output terminal of the CMOS inverter, when an input signal transitions. PMOS and NMOS are used herein to refer to types of transistor.
2. Description of Related Art
Consumption of power has become an important factor limiting a performance of a chip, such as a processor. As a clock speed and a degree of complexity of the chip increase by the development of semiconductor techniques, power demands grow. Therefore, precisely estimating power consumption of the CMOS inverter when designing a semiconductor directly leads to an increased assurance for reliability of the chip and a reduction of design time.
Meanwhile, for a highly complex semiconductor circuit that has a long signal delivery path, operability of a final output terminal of the circuit is enhanced by including a stepped buffer at a signal delivery path and considering the operability at the final output terminal. For enhancing the operability in this context, generally, a buffer is configured as being stepped by connecting CMOS inverter circuits.
However, using the CMOS inverter configuring buffer leads to an issue that a short circuit current is generated when an input signal transitions. That is, a short circuit current is generated when the input level of the input signal changes from a high level to a low level or from a low level to a high level at an input terminal. The short circuit current refers to the phenomenon that a current flows between a power supply terminal and a ground, as a PMOS and an NMOS configured at an output terminal of the CMOS are simultaneously switched on while the input signal transitions as above.
When the short circuit current is generated as described above, the power consumption is unnecessarily increased. The power consumed by such short circuit currents usually does not account for a large part of overall power consumption. However, in situations where the problem of reducing of power efficiency is relevant, such cases frequently happen in which the power used by the short circuit current consumes 20% or more of overall power consumption. In these situations, the power consumption resulting from the short circuit current is more significant and is not negligible.
Further, the short circuit current becomes abnormally high when it operates at the time that the PMOS and NMOS are switched off. Thus, some or all of the circuit elements subjected to the short circuit current might be destroyed or damaged physically. As a result, an output signal that is output from the output terminal of CMOS may not be output stably. In this respect, methods for minimizing the short circuit current at a CMOS inverter would avoid some of these issues.
In an example, an approach to minimize short circuit current is disclosed, in which the short circuit current is minimized by simultaneously turning the PMOS and NMOS located at an output terminal off, the moment an input signal transitions.
However, in such an example, when an input signal transitions from a low level to a high level, a gate node of an NMOS is discharged through a transistor M4, and then, a gate node of a PMOS is discharged through a transistor M5 and transistor M4. At this time, the gate node of the PMOS has a feedback loop value which is fed back with a signal from the gate node of the NMOS.
By contrast, when an input signal transitions from a high level to a low level, a gate node of the PMOS is charged through a transistor M2 and a node is discharged as a transistor M3 is turned on, and accordingly, a transistor M6 is turned on. Therefore, a gate node of the NMOS is charged through paths of the transistors M6 and M2. However, even in this case, the gate node of the NMOS has a feedback loop that is fed back with a signal from the gate node of PMOS.
Pursuant to the said example, the example may also be configured to minimize the short circuit current.
Nevertheless, as described so far, the example is configured to require receiving a feedback signal from an opposite node in order for the PMOS 580 and NMOS 590 to be simultaneously off. Therefore, charge and discharge paths have no alternative but to be long due to the receipt issue.
This situation brings about a problem that a working speed of the CMOS inverter reduces. That is, although this example has the characteristic of minimizing the short circuit current, it also has the characteristic that its working speed is reduced due to the use of long charge/discharge paths. Further, power consumption is increasingly generated due to the feedback loop.
Moreover, the example has the characteristic of using a feedback loop. Thus, issues of circuit design becoming more complicated caused by including such a feedback loop and an increase in overall size of such a processor would be associated with such an example.